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74F113 - Dual JK Negative Edge-Triggered Flip-Flop

Description

The 74F113 offers individual J, K, Set and Clock inputs.

When the clock goes HIGH the inputs are enabled and data may be entered.

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Datasheet preview – 74F113

Datasheet Details

Part number 74F113
Manufacturer Fairchild Semiconductor
File Size 59.84 KB
Description Dual JK Negative Edge-Triggered Flip-Flop
Datasheet download datasheet 74F113 Datasheet
Additional preview pages of the 74F113 datasheet.

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Full PDF Text Transcription

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74F113 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised July 1999 74F113 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F113 offers individual J, K, Set and Clock inputs. When the clock goes HIGH the inputs are enabled and data may be entered. The logic level of the J and K inputs may be changed when the clock pulse is HIGH and the flipflop will perform according to the Truth Table as long as minimum setup and hold times are observed. Input data is transferred to the outputs on the falling edge of the clock pulse.
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