74F1071 Datasheet PDF (18-Bit Undershoot/Overshoot Clamp) | Download Fairchild Semiconductor 74F1071

74F1071 - 18-Bit Undershoot/Overshoot Clamp

Description

The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD).

Features

s 18-bit array structure in 20-pin package s FAST® Bipolar voltage clamping action s Dual center pin grounds for min inductance s Robust design for ESD protection s Low input capacitance s Optimum voltage clamping for 5V CMOS/TTL.

Datasheet Details

Part number	74F1071
Manufacturer	Fairchild Semiconductor
File Size	91.84 KB
Description	18-Bit Undershoot/Overshoot Clamp
Datasheet	74F1071 Datasheet
Additional preview pages of the 74F1071 datasheet.

📁 Similar Datasheet

74F10 - Triple 3-input NAND gate (NXP)

74F10 - Triple 3-Input NAND Gate (National Semiconductor)

74F10 - TRIPLE 3-INPUT POSITIVE-NAND GATE (Texas Instruments)

74F109 - Dual JK Positive Edge-Triggered Flip-Flop (National Semiconductor)

74F109 - Positive J-K positive edge-triggered flip-flops (NXP)

74F109 - DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP (Texas Instruments)

74F11 - Triple 3-Input AND Gate (National Semiconductor)

74F11 - Triple 3-input NAND gate (NXP)

74F11 - Triple 3-Input AND Gate (Texas Instruments)

74F112 - Dual J-K negative edge-triggered flip-flop (NXP)

Full PDF Text Transcription

Click to expand full text

74F1071 18-Bit Undershoot/Overshoot Clamp October 1994 Revised August 1999 74F1071 18-Bit Undershoot/Overshoot Clamp and ESD Protection Device General Description The 74F1071 is an 18-bit undershoot/overshoot clamp which is designed to limit bus voltages and also to protect more sensitive devices from electrical overstress due to electrostatic discharge (ESD). The inputs of the device aggressively clamp voltage excursions nominally at 0.5V below and 7V above ground.

Published: Apr 3, 2005 |