74F112 - Dual JK Negative Edge-Triggered Flip-Flop

Description

The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs.

Synchronous state changes are initiated by the falling edge of the clock.

Triggering occurs at a voltage level of the clock and is not directly related to the transition time.

Fairchild Semiconductor

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Datasheet Details

Part number	74F112
Manufacturer	Fairchild Semiconductor
File Size	59.08 KB
Description	Dual JK Negative Edge-Triggered Flip-Flop
Datasheet	74F112 Datasheet
Additional preview pages of the 74F112 datasheet.

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74F112 Dual JK Negative Edge-Triggered Flip-Flop April 1988 Revised July 1999 74F112 Dual JK Negative Edge-Triggered Flip-Flop General Description The 74F112 contains two independent, high-speed JK flipflops with Direct Set and Clear inputs. Synchronous state changes are initiated by the falling edge of the clock. Triggering occurs at a voltage level of the clock and is not directly related to the transition time. The J and K inputs can change when the clock is in either state without affecting the flip-flop, provided that they are in the desired state during the recommended setup and hold times relative to the falling edge of the clock. A LOW signal on SD or CD prevents clocking and forces Q or Q HIGH, respectively. Simultaneous LOW signals on SD and CD force both Q and Q HIGH.

Published: Apr 3, 2005 |