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74F113 - Dual J-K negative edge-triggered flip-flops

Description

The 74F113, dual negative edge-triggered JK-type flip-flop,

Features

  • individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs and data will be accepted. The logic levels at the J and K inputs may be allowed to change while the CP is high and flip-flop will perform according to the function table as long as minimum setup and.

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Datasheet preview – 74F113

Datasheet Details

Part number 74F113
Manufacturer NXP
File Size 81.65 KB
Description Dual J-K negative edge-triggered flip-flops
Datasheet download datasheet 74F113 Datasheet
Additional preview pages of the 74F113 datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS 74F113 Dual J-K negative edge-triggered flip-flops without reset Product specification IC15 Data Handbook 1991 Feb 14 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flops without reset 74F113 FEATURE • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F113, dual negative edge-triggered JK-type flip-flop, features individual J, K, clock (CP), set (SD) inputs, true and complementary outputs. The asynchronous SD input, when low, forces the outputs to the steady state levels as shown in the function table regardless of the level at the other inputs. A high level on the clock (CP) input enables the J and K inputs and data will be accepted.
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