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74F112 - Dual J-K negative edge-triggered flip-flop

Description

The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs.

Features

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Datasheet Details

Part number 74F112
Manufacturer NXP
File Size 83.94 KB
Description Dual J-K negative edge-triggered flip-flop
Datasheet download datasheet 74F112 Datasheet
Additional preview pages of the 74F112 datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS 74F112 Dual J-K negative edge-triggered flip-flop Product specification IC15 Data Handbook 1990 Feb 09 Philips Semiconductors Philips Semiconductors Product specification Dual J-K negative edge-triggered flip-flop 74F112 FEATURE • Industrial temperature range available (–40°C to +85°C) DESCRIPTION The 74F112, Dual Negative Edge-Triggered JK-Type Flip-Flop, feature individual J, K, Clock (CPn), Set (SD) and Reset (RD) inputs, true (Qn) and complementary (Qn) outputs. The SD and RD inputs, when Low, set or reset the outputs as shown in the Function Table, regardless of the level at the other inputs. A High level on the clock (CPn) input enables the J and K inputs and data will be accepted.
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