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74F10 Triple 3-Input NAND Gate
April 1988 Revised July 1999
74F10 Triple 3-Input NAND Gate
General Description
This device contains three independent gates, each of which performs the logic NAND function.
Ordering Code:
Order Number 74F10SC 74F10SJ 74F10PC Package Number M14A M14D N14A Package Description 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
IEEE/IEC
Connection Diagram
Unit Loading/Fan Out
U.L. Pin Names An, Bn, Cn On Description HIGH/LOW Inputs Outputs 1.0/1.0 50/33.
74F10 Datasheet
