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74F109 - Dual JK Positive Edge-Triggered Flip-Flop

This page provides the datasheet information for the 74F109, a member of the 74F109PC Dual JK Positive Edge-Triggered Flip-Flop family.

Description

The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops.

The clocking operation is independent of rise and fall times of the clock waveform.

The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs.

Features

  • n Guaranteed 4000V minimum ESD protection. Ordering Code: See Section 0 Commercial Military 74F109PC 74F109SC (Note 1) 54F109DM (Note 2) 74F109SJ (Note 1) 54F109FM (Note 2) 54F109LM (Note 2) Package Number N16E J16A M16A M16D W16A E20A Package.

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Datasheet preview – 74F109

Datasheet Details

Part number 74F109
Manufacturer National Semiconductor
File Size 133.13 KB
Description Dual JK Positive Edge-Triggered Flip-Flop
Datasheet download datasheet 74F109 Datasheet
Additional preview pages of the 74F109 datasheet.

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Full PDF Text Transcription

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54F/74F109 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop November 1994 54F/74F109 Dual JK Positive Edge-Triggered Flip-Flop General Description The ’F109 consists of two high-speed, completely independent transition clocked JK flip-flops. The clocking operation is independent of rise and fall times of the clock waveform. The JK design allows operation as a D flip-flop (refer to ’F74 data sheet) by connecting the J and K inputs. Asynchronous Inputs: LOW input to SD sets Q to HIGH level LOW input to CD sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on CD and SD makes both Q and Q HIGH Features n Guaranteed 4000V minimum ESD protection.
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