IS45S32400E Datasheet PDF - ISSI 128Mb SYNCHRONOUS DRAM Specs

IS45S32400E - 128Mb SYNCHRONOUS DRAM

This page provides the datasheet information for the IS45S32400E, a member of the IS42S32400E 128Mb SYNCHRONOUS DRAM family.

Datasheet Summary

Description

A0-A11 Row Address Input A0-A7 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command 86 VSS 85 DQ15 84 VSSQ 83 DQ14 82 DQ

Features

Clock frequency: 166, 143, 133 MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Internal bank for hiding row access/precharge.
Single Power supply: 3.3V + 0.3V.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Auto Refresh (CBR).
Self Refresh.
4096 refresh cycles every 16ms (A2 grade) or 6.

Datasheet Details

Part number	IS45S32400E
Manufacturer	ISSI
File Size	694.85 KB
Description	128Mb SYNCHRONOUS DRAM
Datasheet	IS45S32400E Datasheet
Additional preview pages of the IS45S32400E datasheet.

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Full PDF Text Transcription

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IS42S32400E IS45S32400E 4M x 32 128Mb SYNCHRONOUS DRAM NOVEMBER 2010 FEATURES • Clock frequency: 166, 143, 133 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.

Published: May 4, 2016 |