IS45S16160D - 256-MBIT SYNCHRONOUS DRAM

Datasheet Summary

Description

A0-A12 A0-A9 BA0, BA1 DQ0 to DQ7 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM Vdd Vss Vddq Vssq NC Write Enable Data Input

Features

Clock frequency: 166, 143 MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Internal bank for hiding row access/precharge.
Single Power supply: 3.3V + 0.3V.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Auto Refresh (CBR).
Self Refresh.
8K refresh cycles every 16 ms (A2 grade) or 64 ms (com.

Integrated Silicon Solution

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Datasheet Details

Part number	IS45S16160D
Manufacturer	Integrated Silicon Solution
File Size	915.75 KB
Description	256-MBIT SYNCHRONOUS DRAM
Datasheet	IS45S16160D Datasheet
Additional preview pages of the IS45S16160D datasheet.

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Full PDF Text Transcription

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IS42S83200D, IS42S16160D IS45S83200D, IS45S16160D www.DataSheet4U.com 32Meg x 8, 16Meg x16 JUNE 2009 256-MBIT SYNCHRONOUS DRAM FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.

Published: Apr 30, 2010 |