IS45S32160B Datasheet PDF - ISSI 512Mb SYNCHRONOUS DRAM Specs

IS45S32160B - 512Mb SYNCHRONOUS DRAM

Datasheet Summary

Description

A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ31 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command 86 VSS 85 DQ15 84 VSSQ 83 DQ14 82 DQ13

Features

Clock frequency: 166, 143 MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Internal bank for hiding row access/precharge.
Single Power supply: 3.3V + 0.3V.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Auto Refresh (CBR).
Self Refresh.
8192 refresh cycles every 16ms (A2 grade) or 64 ms (Com.

Datasheet Details

Part number	IS45S32160B
Manufacturer	ISSI
File Size	745.39 KB
Description	512Mb SYNCHRONOUS DRAM
Datasheet	IS45S32160B Datasheet
Additional preview pages of the IS45S32160B datasheet.

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Full PDF Text Transcription

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IS42S32160B IS45S32160B 16M x 32 512Mb SYNCHRONOUS DRAM PRELIMINARY INFORMATION JULY 2009 FEATURES • Clock frequency: 166, 143 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 3.3V + 0.

Published: May 4, 2016 |