IS45S32400B Datasheet PDF - ISSI 128-MBIT SYNCHRONOUS DRAM Specs

IS45S32400B - 128-MBIT SYNCHRONOUS DRAM

Datasheet Summary

Description

A0-A11 A0-A7 BA0, BA1 DQ0 to DQ31 CLK CKE CS RAS CAS Row Address Input Column Address Input Bank Select Address Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command WE DQM0-DQM3 VDD Vss VDDQ VssQ NC Write Enable x32 Input/Output Mask Powe

Features

Clock frequency: 166, 143, 125, 100 MHz.
Fully synchronous; all signals referenced to a positive clock edge.
Internal bank for hiding row access/precharge.
Power supply IS45S32400B VDD VDDQ 3.3V 3.3V.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Auto Refresh (CBR).
Self Refresh with programmable refresh periods.

Datasheet Details

Part number	IS45S32400B
Manufacturer	ISSI
File Size	618.32 KB
Description	128-MBIT SYNCHRONOUS DRAM
Datasheet	IS45S32400B Datasheet
Additional preview pages of the IS45S32400B datasheet.

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Full PDF Text Transcription

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IS45S32400B 4Meg x 32 128-MBIT SYNCHRONOUS DRAM ISSI® JULY 2006 FEATURES • Clock frequency: 166, 143, 125, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Power supply IS45S32400B VDD VDDQ 3.3V 3.

Published: May 4, 2016 |