AS4C256M16D3LA-12BIN Datasheet PDF - Alliance Semiconductor 256M x 16 bit DDR3L Synchronous DRAM Specs

AS4C256M16D3LA-12BIN - 256M x 16 bit DDR3L Synchronous DRAM

Datasheet Summary

Features

JEDEC Standard Compliant.
Power supplies: VDD & VDDQ = +1.35V.
Backward compatible to VDD & VDDQ = 1.5V ±0.075V.
Operating temperature: -40~95°C (TC).
Supports JEDEC clock jitter specification.
Fully synchronous operation.
Fast clock rate: 800 MHz.
Differential Clock, CK & CK#.
Bidirectional differential data strobe - DQS & DQS#.
8 internal banks for concurrent operation.
8n-bit prefetch architect.

Datasheet Details

Part number	AS4C256M16D3LA-12BIN
Manufacturer	Alliance Semiconductor
File Size	2.17 MB
Description	256M x 16 bit DDR3L Synchronous DRAM
Datasheet	AS4C256M16D3LA-12BIN Datasheet
Additional preview pages of the AS4C256M16D3LA-12BIN datasheet.

📁 Similar Datasheet

AS4C1024 - 1M x 1 DRAM (Austin Semiconductor)

AS4C1259 - 256K x 1 DRAM (Austin Semiconductor)

AS4C1259883C - 256K x 1 DRAM (Austin Semiconductor)

AS4C1M16S - 1M x 16 bit Synchronous DRAM (Alliance Memory)

AS4C1M16S-C - 1M x 16 bit Synchronous DRAM (Alliance Memory)

AS4C1M16S-I - 1M x 16 bit Synchronous DRAM (Alliance Memory)

AS4C4067 - 64K x 4 DRAM (Austin Semiconductor)

AS4C4256 - (Austin Semiconductor)

AS4C4256883C - 256K x 4 DRAM (Austin Semiconductor)

AS4C4M4 - 16M FPM DRAM (Austin Semiconductor)

Full PDF Text Transcription

Click to expand full text

AS4C256M16D3LA-12BIN Revision History 4Gb AS4C256M16D3LA-12BIN - 96 ball FBGA PACKAGE Revision Details Rev 1.0 Preliminary datasheet Date May. 2016 Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211 Alliance Memory Inc. reserves the right to change products or specification without notice Confidential -183- Rev. 1.0 May 2016 AS4C256M16D3LA-12BIN 256M x 16 bit DDR3L Synchronous DRAM (SDRAM) Features • JEDEC Standard Compliant • Power supplies: VDD & VDDQ = +1.35V • Backward compatible to VDD & VDDQ = 1.5V ±0.

Published: Oct 13, 2019 |