AS4C256M16D3L Datasheet PDF - Alliance Semiconductor 256M x 16 bit DDR3L Synchronous DRAM Specs

AS4C256M16D3L - 256M x 16 bit DDR3L Synchronous DRAM

Datasheet Summary

Features

JEDEC Standard Compliant.
Power supplies: VDD & VDDQ = +1.35V.
Backward compatible: VDD & VDDQ = 1.5V +/- 0.075V.
Operating temperature: - Commercial (0 ~ 95°C) - Industrial (-40 ~ 95°C).
Supports JEDEC clock jitter specification.
Fully synchronous operation.
Fast clock rate: 800MHz.
Differential Clock, CK & CK#.
Bidirectional differential data strobe -DQS & DQS#.
8 internal banks for concurrent operation.
8n-bit prefetch architecture.

Datasheet Details

Part number	AS4C256M16D3L
Manufacturer	Alliance Semiconductor
File Size	2.04 MB
Description	256M x 16 bit DDR3L Synchronous DRAM
Datasheet	AS4C256M16D3L Datasheet
Additional preview pages of the AS4C256M16D3L datasheet.

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Full PDF Text Transcription

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4Gb DDR3L – AS4C256M16D3L Revision History AS4C256M16D3L - 96-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Added "Backward compatible to VDD & VDDQ = 1.5V +/0.075V" - page 2 Added CL=5 & CL=6 to Table 18 – page 31 Updated Table 12. Recommended DC Operating Conditions – page 26 Date April 2014 August 2014 Confidential 1 Rev. 2.0 Aug. /2014 4Gb DDR3L -AS4C256M16D3L Confidential 256M x 16 bit DDR3L Synchronous DRAM (SDRAM) Advanced (Rev. 2.0, Aug. /2014) Features  JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.35V  Backward compatible: VDD & VDDQ = 1.5V +/- 0.

Published: Oct 13, 2019 |