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PCS3P625Z05C Datasheet, PulseCore Semiconductor

PCS3P625Z05C ic equivalent, low frequency timing-safe peak emi reduction ic.

PCS3P625Z05C Avg. rating / M : 1.0 rating-11

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PCS3P625Z05C Datasheet

Features and benefits


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* High Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 100MHz - 175MHz Multiple low skew Timing-safe™ Outputs: PCS.

Application

requiring zero input-output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used.

Description

PCS3P625Z05/09 is a versatile, 3.3V Zero-delay buffer designed to distribute high frequency Timing-Safe™ clocks memory interface systems. General Block Diagram PLL CLKIN DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3 CLKIN PLL MUX DLY_CTRL CLKOUTA1 CLKOUTA2.

Image gallery

PCS3P625Z05C Page 1 PCS3P625Z05C Page 2 PCS3P625Z05C Page 3

TAGS

PCS3P625Z05C
Low
Frequency
Timing-Safe
Peak
EMI
reduction
PulseCore Semiconductor

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