PCS3P623Z05A ic equivalent, timing-safe peak emi reduction ic.
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* Clock distribution with Timing-Safe™ Peak EMI Reduction Input frequency range: 20MHz - 50MHz Multiple low skew Timing-safe™ Outputs: PCS3P623Z05: 5 Outp.
requiring zero input-output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used.
PCS3P623Z05/09 is a versatile, 3.3V Zero-delay buffer
memory interface systems.
General Block Diagram
PLL CLKIN
DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3
PLL CLKIN
MUX
DLY_CTRL CLKOUTA1 CLKOUTA2 CLKOUTA3 CLKOUTA4
PCS3P623Z05A/B
CLKOUT4 S2 S1 Select I.
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