PCS3P622Z05C ic equivalent, low frequency timing-safe peak emi reduction ic.
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* Low Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 4MHz - 20MHz Multiple low skew Timing-safe™ Outputs: PCS3P62.
requiring zero input-output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used.
PCS3P622Z05/09 is a versatile, 3.3V Zero-delay buffer
General Block Diagram
PLL CLKIN
DLY_CTRL CLKOUT1 CLKOUT2 CLKIN
PLL
MUX
DLY_CTRL CLKOUTA1 CLKOUTA2 CLKOUTA3
CLKOUT3
CLKOUTA4 S2 S1 CLKOUTB1 Select Input Decoding CLKOUTB2 CLKOUTB3
PCS3P622.
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