PCS3P624Z05B ic equivalent, low frequency timing-safe peak emi reduction ic.
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* High Frequency Clock distribution with TimingSafe™ Peak EMI Reduction Input frequency range: 50MHz - 100MHz Multiple low skew Timing-safe™ Outputs: PCS3.
requiring zero input-output delay, all outputs, including DLY_CTRL, must be equally loaded. Even if DLY_CTRL is not used.
PCS3P624Z05/09 is a versatile, 3.3V Zero-delay buffer designed to distribute high frequency Timing-Safe™ clocks
memory interface systems.
General Block Diagram
PLL CLKIN
DLY_CTRL CLKOUT1 CLKOUT2 CLKOUT3
PLL CLKIN
MUX
DLY_CTRL CLKOUTA1 CLKOUTA2.
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