PLL102-109 driver equivalent, programmable ddr zero delay clock driver.
PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz.
* Distributes one clock Input to one bank of six differential outputs.
* Tra.
The PLL102-109 is a zero delay buffer that distributes a single-ended clock input to six pairs of differential clock outputs and one feedback clock output. Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT. The .
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