PLL102-15 buffer equivalent, low skew output buffer.
Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).
.
requiring zero output-output skew, all the outputs must equally loaded.
www.DataSheet4U.com
If the CLK(1-3) outputs are.
The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package. It has four outputs that are synchronized with the input. The synchronization is.
Image gallery
TAGS
Download (Size : 141.06KB)