Datasheet4U Logo Datasheet4U.com

PLL102-108 - Programmable DDR Zero Delay Clock Driver

Description

The PLL102-108 is a zero delay buffer that distributes a single-ended clock input to ten pairs of differential clock outputs and one feedback clock output.

Output signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK_INT.

Features

  • PLL clock distribution optimized for Double Data Rate SDRAM.

📥 Download Datasheet

Datasheet Details

Part number PLL102-108
Manufacturer PhaseLink Corporation
File Size 198.33 KB
Description Programmable DDR Zero Delay Clock Driver
Datasheet download datasheet PLL102-108 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
PLL1000A PHASE LOCKED LOOP Z-Communications
PLL1070A PHASE LOCKED LOOP Z-Communications
PLL1700 MULTI-CLOCK GENERATOR Burr-Brown
PLL1705 3.3-V DUAL PLL MULTICLOCK GENERATOR Burr-Brown
PLL1706 3.3-V DUAL PLL MULTICLOCK GENERATOR Burr-Brown

Other Datasheets by PhaseLink Corporation

Part Number Description
PLL102-10 Low Skew Output Buffer
PLL102-109 Programmable DDR Zero Delay Clock Driver
PLL102-15 Low Skew Output Buffer
PLL102-03 Low Skew Output Buffer
PLL102-04 Low Skew Output Buffer

Full PDF Text Transcription

Click to expand full text
PLL102-108 Programmable DDR Zero Delay Clock Driver FEATURES PLL clock distribution optimized for Double Data Rate SDRAM application up to 266Mhz. • Distributes one clock Input to one bank of ten differential outputs. • Track spread spectrum clocking for EMI reduction. • Programmable delay between CLK_INT and CLK[T/C] from –0.8ns to +3.1ns by programming www.DataSheet4U.com CLKINT and FBOUT skew channel, or from –1.1ns to +3.5ns if additional DDR skew channels are enabled. • Four independent programmable DDR skew channels from –0.3ns to +0.4ns with step size ± 100ps. • Support 2-wire I2C serial bus interface. • 2.5V Operating Voltage. • Available in 48-Pin 300mil SSOP.
Published: |