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PLL102-15 - Low Skew Output Buffer

Description

The PLL102 -15 is a high performance, low skew, low jitter zero delay buffer designed to di stribute high speed clocks and is available in 8 -pin SOIC or TSSOP package.

It has four outputs that are synchronized with the input.

Features

  • Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation).
  • Zero input - output delay.
  • Less than 700 ps device - device skew.
  • Less than 250 ps skew between outputs. www. DataSheet4U. com.
  • Less than 200 ps cycle - cycle jitter.
  • Output Enable function tri -state outputs.
  • 3.3V operation.
  • Available in 8 -Pin 150mil SOIC.

📥 Download Datasheet

Datasheet Details

Part number PLL102-15
Manufacturer PhaseLink Corporation
File Size 141.06 KB
Description Low Skew Output Buffer
Datasheet download datasheet PLL102-15 Datasheet

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Other Datasheets by PhaseLink Corporation

Part Number Description
PLL102-10 Low Skew Output Buffer
PLL102-108 Programmable DDR Zero Delay Clock Driver
PLL102-109 Programmable DDR Zero Delay Clock Driver
PLL102-03 Low Skew Output Buffer
PLL102-04 Low Skew Output Buffer

Full PDF Text Transcription

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PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250 ps skew between outputs. www.DataSheet4U.com • Less than 200 ps cycle - cycle jitter. • Output Enable function tri -state outputs. • 3.3V operation. • Available in 8 -Pin 150mil SOIC. • • PIN CONFIGURATION VDD CLK1 CLKOUT GND 1 2 3 4 8 7 6 5 N/C CLK3 CLK2 REF_IN PLL102-15 Remark If REF_IN clock is stopped for more than 10us after it has already been provided to the chip, and after power-up, the output clocks will disappear.
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