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PLL1705 - 3.3-V DUAL PLL MULTICLOCK GENERATOR

Download the PLL1705 datasheet PDF. This datasheet also covers the PLL1706_Burr variant, as both devices belong to the same 3.3-v dual pll multiclock generator family and are provided as variant models within a single manufacturer datasheet.

Description

The PLL1705† and PLL1706† are low cost, phase-locked loop (PLL) multiclock generators.

The PLL1705 and PLL1706 can generate four system clocks from a 27-MHz reference input frequency.

Features

  • D 27-MHz Master Clock Input D Generated Audio System Clock: www. DataSheet4U. com.
  • SCKO0: 768 fS (fS = 44.1 kHz).
  • SCKO1: 384 fS, 768 fS (fS = 44.1 kHz).
  • SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz).
  • SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz).

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (PLL1706_Burr-Brown.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription

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PLL1705 PLL1706 SLES046A – AUGUST 2002 – REVISED SEPTEMBER 2002 3.3-V DUAL PLL MULTICLOCK GENERATOR FEATURES D 27-MHz Master Clock Input D Generated Audio System Clock: www.DataSheet4U.com – SCKO0: 768 fS (fS = 44.1 kHz) – SCKO1: 384 fS, 768 fS (fS = 44.1 kHz) – SCKO2: 256 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) – SCKO3: 384 fS (fS = 32, 44.1, 48, 64, 88.2, 96 kHz) APPLICATIONS D DVD Players D DVD Add-On Cards for Multimedia PCs D Digital HDTV Systems D Set-Top Boxes DESCRIPTION The PLL1705† and PLL1706† are low cost, phase-locked loop (PLL) multiclock generators. The PLL1705 and PLL1706 can generate four system clocks from a 27-MHz reference input frequency.
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