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PLL102-04 - Low Skew Output Buffer

Description

The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package.

It has four outputs that are synchronized with the input.

The synchronization is established via CLKOUT feed back to the input of the PLL.

Features

  • Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
  • Zero input - output delay.
  • Less than 700 ps device - device skew.
  • Less than 250 ps skew between outputs. www. DataSheet4U. com.
  • Less than 200 ps cycle - cycle jitter.
  • Output Enable function tri-state outputs.
  • 3.3V operation.
  • Available in 8-Pin 150mil SOIC.

📥 Download Datasheet

Datasheet Details

Part number PLL102-04
Manufacturer PhaseLink Corporation
File Size 269.36 KB
Description Low Skew Output Buffer
Datasheet download datasheet PLL102-04 Datasheet

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Other Datasheets by PhaseLink Corporation

Part Number Description
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Full PDF Text Transcription

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PLL102-04 Low Skew Output Buffer FEATURES Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250 ps skew between outputs. www.DataSheet4U.com • Less than 200 ps cycle - cycle jitter. • Output Enable function tri-state outputs. • 3.3V operation. • Available in 8-Pin 150mil SOIC. • • PIN CONFIGURATION REF CLK2 CLK1 GND 1 2 3 4 8 7 6 5 CLKOUT CLK4 VDD CLK3 PLL102-04 DESCRIPTION The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input.
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