900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf






PhaseLink Corporation

PLL102-10 Datasheet Preview

PLL102-10 Datasheet

Low Skew Output Buffer

No Preview Available !

PLL102-10
Low Skew Output Buffer
FEATURES
Frequency range 50 ~ 120MHz.
Internal phase locked loop will allow spread spec-
trum modulation on reference clock to pass to out-
puts.
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs.
www.DataSheet4U.Lceomss than 100 ps cycle - cycle jitter.
2.5V or 3.3V power supply operation.
Available in 8-Pin SOIC or MSOP package.
PIN CONFIGURATION
REFIN
GND
CLK1
CLK2
1
2
3
4
8
7
6
5
CLKOUT
DNC
DNC
VDD
DESCRIPTION
The PLL102-10 is a high performance, low skew, low
jitter zero delay buffer designed to distribute high
speed clocks and is available in 8-pin SOIC or MSOP
package. It has two outputs that are synchronized with
the input. The synchronization is established via
CLKOUT feed back to the input of the PLL. Since the
skew between the input and output is less than ±350
ps, the device acts as a zero delay buffer.
BLOCK DIAGRAM
REFIN
PLL
CLKOUT
CLK1
CLK2
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/22/05 Page 1




PhaseLink Corporation

PLL102-10 Datasheet Preview

PLL102-10 Datasheet

Low Skew Output Buffer

No Preview Available !

PIN DESCRIPTIONS
Name
Number
REFIN
GND
CLK1
CLK2
VDD
www.DataSheet4U.com
DNC
CLKOUT2
1
2
3
4
5
6&7
8
PLL102-10
Low Skew Output Buffer
Type
I
P
O
O
P
-
O
Description
Input reference frequency. Spread spectrum modulation on this signal will be
passed to the output (up to 100kHz SST modulation).
Ground Connection.
Buffered clock output.
Buffered clock output.
2.5V or 3.3V Power Supply connection.
Do Not Connect
Buffered clock output. Internal feed back on this pin.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
VDD 4.6 V
VI
-0.5 VDD+0.5
V
VO
-0.5 VDD+0.5
V
TS -65 150 °C
TA -40 85 °C
TJ 125 °C
260 °C
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Electrical Characteristics
PARAMETERS
Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Supply Current
SYMBOL
VDD
VIL
VIH
VOL
VOH
IDD
CONDITIONS
IOL = 24mA
IOH = 24mA
Unloaded outputs at 100MHz,
VDD=3.3V.
MIN.
2.25
2.0
2.4
TYP.
22
MAX.
3.63
0.8
0.4
30
UNITS
V
V
V
V
V
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 03/17/05 Page 2


Part Number PLL102-10
Description Low Skew Output Buffer
Maker PhaseLink Corporation
Total Page 6 Pages
PDF Download

PLL102-10 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 PLL102-10 Low Skew Output Buffer
PhaseLink Corporation
2 PLL102-108 Programmable DDR Zero Delay Clock Driver
PhaseLink Corporation
3 PLL102-109 Programmable DDR Zero Delay Clock Driver
PhaseLink Corporation
4 PLL102-15 Low Skew Output Buffer
PhaseLink Corporation





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy