PLL102-10 buffer equivalent, low skew output buffer.
Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.
* Zero input - output delay.
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requiring zero output-output skew, all the outputs must be equally loaded.
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If the CLK(1-2) outputs .
The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package. It has two outputs that are synchronized with the input. The synchronization is estab.
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