PLL102-10 - Low Skew Output Buffer

PhaseLink Corporation

Datasheet Details

Part number	PLL102-10
Manufacturer	PhaseLink Corporation
File Size	213.29 KB
Description	Low Skew Output Buffer
Datasheet	PLL102-10 Datasheet

General Description

The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package.

It has two outputs that are synchronized with the input.

The synchronization is established via CLKOUT feed back to the input of the PLL.

Overview

PLL102-10 Low Skew Output Buffer.

Key Features

Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs. www. DataSheet4U. com.
Less than 100 ps cycle - cycle jitter.
2.5V or 3.3V power supply operation.
Available in 8-Pin SOIC or MSOP package.
PIN.

More Datasheets from PhaseLink Corporation

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PLL103-04	1-to-4 Clock Distribution Buffer