PLL102-10 - Low Skew Output Buffer

Product Overview

PhaseLink Corporation

Datasheet Details

Part number	PLL102-10
Manufacturer	PhaseLink Corporation
File Size	213.29 KB
Description	Low Skew Output Buffer
Datasheet	PLL102-10 Datasheet
Additional preview pages of the PLL102-10 datasheet.

Product details

Description

The PLL102-10 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC or MSOP package.

Features

Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to outputs.
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs. www. DataSheet4U. com.
Less than 100 ps cycle - cycle jitter.
2.5V or 3.3V power supply operation.
Available in 8-Pin SOIC or MSOP package.
PIN.

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Other Datasheets by PhaseLink Corporation

PLL102-108 - Programmable DDR Zero Delay Clock Driver
PLL102-109 - Programmable DDR Zero Delay Clock Driver
PLL102-15 - Low Skew Output Buffer
PLL102-03 - Low Skew Output Buffer
PLL102-04 - Low Skew Output Buffer
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Published: Oct 28, 2008 |