PLL102-04 buffer equivalent, low skew output buffer.
Frequency range 50 ~ 120MHz. Internal phase locked loop will allow spread spectrum modulation on reference clock to pass to the outputs (up to 100kHz SST modulation).
requiring zero output-output skew, all the outputs must equally loaded.
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If the CLK(1-4) outputs are.
The PLL102-04 is a high performance, low skew, low jitter zero delay buffer designed to distribute high speed clocks and is available in 8-pin SOIC package. It has four outputs that are synchronized with the input. The synchronization is established .
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