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PhaseLink Corporation

PLL102-03 Datasheet Preview

PLL102-03 Datasheet

Low Skew Output Buffer

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PLL102-03
Low Skew Output Buffer
FEATURES
Frequency range 75 ~ 180MHz.
Internal phase locked loop will allow spread spec-
trum modulation on reference clock to pass to the
outputs (up to 100kHz SST modulation).
Zero input - output delay.
Less than 700 ps device - device skew.
Less than 250 ps skew between outputs.
www.DataSheet4U.Lceomss than 150 ps cycle - cycle jitter.
Output Enable function tri-state outputs.
3.3V operation.
Available in 8-Pin 150mil SOIC GREEN package.
DESCRIPTION
The PLL102-03 is a high performance, low skew, low
jitter zero delay buffer designed to distribute high
speed clocks and is available in an 8-pin SOIC pack-
age. It has four outputs that are synchronized with the
input. The synchronization is established via CLKOUT
feed back to the input of the PLL. Since the skew be-
tween the input and output is less than ±350 ps, the
device acts as a zero delay buffer.
BLOCK DIAGRAM
PIN CONFIGURATION
REF
CLK2
CLK1
GND
1
2
3
4
8 CLKOUT
7 CLK4
6 VDD
5 CLK3
Remark
If REF clock is stopped for more than 10us after it has already been
provided to the chip, and after power-up, the output clocks will
disappear. In that instance, a full power-up reset is required in order
to reactivate the output clocks.
REF
PLL
CLKOUT
CLK1
CLK2
CLK3
CLK4
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 1




PhaseLink Corporation

PLL102-03 Datasheet Preview

PLL102-03 Datasheet

Low Skew Output Buffer

No Preview Available !

PLL102-03
Low Skew Output Buffer
PIN DESCRIPTIONS
Name
Number Type
Description
REF1
CLK22
CLK12
GND
CLK32
www.DataSheet4U.com
VDD
CLK42
CLKOUT2
1
I
Input reference frequency. Spread spectrum modulation on this signal will be
passed to the output (up to 100kHz SST modulation).
2 O Buffered clock output.
3 O Buffered clock output.
4 P Ground.
5 O Buffered clock output.
6 P 3.3V Power Supply.
7 O Buffered clock output.
8 O Buffered clock output. Internal feed back on this pin.
Notes: 1: Weak pull-down. 2: Weak pull-down on all outputs.
ELECTRICAL SPECIFICATIONS
1. Absolute Maximum Ratings
PARAMETERS
SYMBOL
MIN.
MAX.
UNITS
Supply Voltage
Input Voltage, dc
Output Voltage, dc
Storage Temperature
Ambient Operating Temperature*
Junction Temperature
Lead Temperature (soldering, 10s)
ESD Protection, Human Body Model
VDD 4.6 V
VI
-0.5 VDD+0.5
V
VO
-0.5 VDD+0.5
V
TS -65 150 °C
TA -40 85 °C
TJ 125 °C
260 °C
2 kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other con-
ditions above the operational limits noted in this specification is not implied.
* Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
2. Electrical Characteristics
PARAMETERS
Supply Voltage
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Power Down Supply Current
Supply Current
SYMBOL
VDD
VIL
VIH
IIL
IIH
VOL
VOH
IDD
IDD
CONDITIONS
VIN = 0V
VIN = VDD
IOL = 50mA
IOH = 50mA
REF = 0MHz
Unloaded outputs at 133MHz,
SEL inputs at VDD or GND
MIN.
2.97
2.0
2.4
TYP.
19
0.10
0.25
2.9
0.3
35
MAX.
3.63
0.8
50.0
100.0
0.4
50.0
45
UNITS
V
V
V
µA
µA
V
V
µA
mA
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 02/23/06 Page 2


Part Number PLL102-03
Description Low Skew Output Buffer
Maker PhaseLink Corporation
Total Page 6 Pages
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