CY7C1371KVE33 Features
* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Data is transferred on every clock
* Pin-compatible and functionally equivalent to ZBT™ devices
* Internally self-timed outp
CY7C1371KV33-CypressSemiconductor.pdf
Datasheet Details
CY7C1371KVE33, CY7C1371KV33
Cypress Semiconductor
0.96 MB
18-mbit (512k x 36/1m x 18) flow-through sram.
This datasheet PDF includes multiple part numbers: CY7C1371KVE33, CY7C1371KV33.
Please refer to the document for exact specifications by model.
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CY7C1371KVE33 Distributor
