CY7C1371C Datasheet | Cypress

Features - No Bus Latency™ (No BL™) architecture eliminates dead cycles between write and read cycles - Can support up to 133-MHz bus operations with zero wait states - Data is transferred on every clock - Pin patible and functionally equivalent to ZBT™ devices - Internally self-timed output buffer control to eliminate the need to use OE - Registered inputs for flow-through operation - Byte Write capability - 3.3V/2.5V I/O power supply - Fast clock-to-output times - 6.5 ns (for 133-MHz device) - 7.5 ns (for 117-MHz device) - 8.5 ns (for 100-MHz device) - Clock Enable (CEN) pin to enable clock and suspend operation - Synchronous self-timed writes - Asynchronous Output Enable - Offered in JEDEC-standard 100 TQFP, 119-Ball BGA and 165-Ball f BGA packages - Three chip enables for simple depth expansion - Automatic Power-down feature available using ZZ mode or CE deselect - JTAG boundary scan for BGA and f BGA packages - Burst Capability- linear or interleaved burst order - Low standby power Functional Description [1] The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371C/ CY7C1373C is equipped with the advanced No Bus Latency™ (No BL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent Write-Read transitions. All synchronous inputs pass through input registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Maximum access delay from the clock rise is 6.5 ns (133-MHz device). Write operations are controlled by the two or four Byte Write Select (BWX) and a Write Enable (WE) input. All writes are...