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CY7C1371C - 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture

The CY7C1371C by Cypress is a 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture. Below is the official datasheet preview.

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Official preview page of the CY7C1371C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture datasheet (Cypress).

Datasheet Details

Part number CY7C1371C
Manufacturer Cypress
File Size 791.68 KB
Description 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL Architecture
Datasheet download datasheet CY7C1371C_Cypress.pdf
Additional preview pages of the CY7C1371C datasheet.

CY7C1371C Product details

Description

1] The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.The CY7C1371C/ CY7C1373C is equipped with the advanced No Bus Latency™ (NoBL™) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.This feature dramatically improves the throughput of data through the SRAM, especially in systems

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