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CY7C1371C Datasheet Cypress

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Cypress · CY7C1371C File Size : 791.68KB · 2 hits

Features and Benefits


• No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self-timed output buffer control.

CY7C1371C CY7C1371C CY7C1371C
TAGS
18-Mbit
512K
Flow-Through
SRAM
with
NoBL
Architecture
CY7C1371B
CY7C1371C
CY7C1371D
Stock and Price
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