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CY7C1371D - 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM

This page provides the datasheet information for the CY7C1371D, a member of the CY7C1373D 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM family.

Datasheet Summary

Description

The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion.

Features

  • No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles.
  • Supports up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin-compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow through operation.
  • Byte write capability.
  • 3.3 V/2.5 V I/O power supply (VDDQ).
  • Fast clock-to-output ti.

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Datasheet preview – CY7C1371D

Datasheet Details

Part number CY7C1371D
Manufacturer Cypress Semiconductor
File Size 802.19 KB
Description 18-Mbit (512 K x 36/1 M x 18) Flow-Through SRAM
Datasheet download datasheet CY7C1371D Datasheet
Additional preview pages of the CY7C1371D datasheet.

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Full PDF Text Transcription

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CY7C1371D CY7C1373D 18-Mbit (512 K × 36/1 M × 18) Flow-Through SRAM with NoBL™ Architecture 18-Mbit (512 K × 36/1 M × 18) Flow-through SRAM with NoBL™ Architecture Features ■ No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles ■ Supports up to 133-MHz bus operations with zero wait states ❐ Data is transferred on every clock ■ Pin-compatible and functionally equivalent to ZBT™ devices ■ Internally self-timed output buffer control to eliminate the need to use OE ■ Registered inputs for flow through operation ■ Byte write capability ■ 3.3 V/2.5 V I/O power supply (VDDQ) ■ Fast clock-to-output times ❐ 6.
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