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CY7C1371DV25 - (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM

This page provides the datasheet information for the CY7C1371DV25, a member of the CY7C1373DV25 (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM family.

Datasheet Summary

Description

The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x 36/1M x 18 Synchronous Flow-through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations without the insertion of wait states.

Features

  • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles.
  • Can support up to 133-MHz bus operations with zero wait states.
  • Data is transferred on every clock.
  • Pin compatible and functionally equivalent to ZBT™ devices.
  • Internally self-timed output buffer control to eliminate the need to use OE.
  • Registered inputs for flow-through operation.
  • Byte Write capability.
  • 2.5V core power supply (VDD).

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Datasheet preview – CY7C1371DV25

Datasheet Details

Part number CY7C1371DV25
Manufacturer Cypress Semiconductor
File Size 486.89 KB
Description (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
Datasheet download datasheet CY7C1371DV25 Datasheet
Additional preview pages of the CY7C1371DV25 datasheet.

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Full PDF Text Transcription

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CY7C1371DV25 www.DataSheet4U.com CY7C1373DV25 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features • No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ devices • Internally self-timed output buffer control to eliminate the need to use OE • Registered inputs for flow-through operation • Byte Write capability • 2.5V core power supply (VDD) • 2.5V I/O power supply (VDDQ) • Fast clock-to-output times — 6.
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