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Cypress Semiconductor Electronic Components Datasheet

CY7C1370C Datasheet

512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

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CY7C1370C
CY7C1372C
512K x 36/1M x 18 Pipelined SRAM
with NoBL™ Architecture
Features
• Pin-compatible and functionally equivalent to ZBT™
• Supports 250-MHz bus operations with zero wait states
— Available speed grades are 250, 225, 200 and
167 MHz
• Internally self-timed output buffer control to eliminate
the need to use asynchronous OE
• Fully registered (inputs and outputs) for pipelined
operation
• Byte Write capability
• Single 3.3V power supply
• 3.3V/2.5V I/O power supply
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
— 2.8 ns (for 225-MHz device)
— 3.0 ns (for 200-MHz device)
— 3.4 ns (for 167-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Available in 100 TQFP, 119 BGA, and 165 fBGA
packages
• IEEE 1149.1 JTAG Boundary Scan
• Burst capability—linear or interleaved burst order
• “ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1370C and CY7C1372C are 3.3V, 512K x 36 and
1M x 18 Synchronous pipelined burst SRAMs with No Bus
Latency™ (NoBL) logic, respectively. They are designed to
support unlimited true back-to-back Read/Write operations
with no wait states. The CY7C1370C and CY7C1372C are
equipped with the advanced (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data in systems that require frequent
Write/Read transitions. The CY7C1370C and CY7C1372C are
pin compatible and functionally equivalent to ZBT devices.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which when deasserted suspends operation and extends the
previous clock cycle.
Write operations are controlled by the Byte Write Selects
(BWa–BWd for CY7C1370C and BWa–BWb for CY7C1372C)
and a Write Enable (WE) input. All writes are conducted with
on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to avoid bus
contention, the output drivers are synchronously three-stated
during the data portion of a write sequence.
Logic Block Diagram-CY7C1370C (512K x 36)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BWa
BWb
BWc
BWd
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
D
A
T
A
S
T
E
E
R
I
N
O
U
T
P
U
T
B
U
F
F
E
R
S
E
G
DQs
DQPa
DQPb
DQPc
DQPd
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
OE
CE1 READ LOGIC
CE2
CE3
ZZ SLEEP
CONTROL
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05233 Rev. *D
Revised June 03, 2004


Cypress Semiconductor Electronic Components Datasheet

CY7C1370C Datasheet

512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

No Preview Available !

Logic Block Diagram-CY7C1372C (1M x 18)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
LOGIC
ADV/LD
C
WRITE ADDRESS
REGISTER 2
CY7C1370C
CY7C1372C
ADV/LD
BWa
BWb
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER 1 E
INPUT
REGISTER 0 E
DQs
DQPa
DQPb
OE
CE1
CE2
CE3
ZZ
READ LOGIC
Sleep
Control
Selection Guide
CY7C1370C-250 CY7C1370C-225 CY7C1370C-200 CY7C1370C-167
CY7C1372C-250 CY7C1372C-225 CY7C1372C-200 CY7C1372C-167
Maximum Access Time
2.6 2.8 3.0 3.4
Maximum Operating Current
350 325 300 275
Maximum CMOS Standby Current
70
70
70
70
Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts.
Unit
ns
mA
mA
Document #: 38-05233 Rev. *D
Page 2 of 27


Part Number CY7C1370C
Description 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture
Maker Cypress
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CY7C1370C Datasheet PDF






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