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CY7C1370C Datasheet 512K x 36/1M x 18 Pipelined SRAM with NoBL Architecture

Manufacturer: Cypress (now Infineon)

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General Description

The CY7C1370C and CY7C1372C are 3.3V, 512K x 36 and 1M x 18 Synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL) logic, respectively.

They are designed to support unlimited true back-to-back Read/Write operations with no wait states.

The CY7C1370C and CY7C1372C are equipped with the advanced (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.

Overview

CY7C1370C CY7C1372C 512K x 36/1M x 18 Pipelined SRAM with NoBL™.

Key Features

  • Pin-compatible and functionally equivalent to ZBT™.
  • Supports 250-MHz bus operations with zero wait states.
  • Available speed grades are 250, 225, 200 and 167 MHz.
  • Internally self-timed output buffer control to eliminate the need to use asynchronous OE.
  • Fully registered (inputs and outputs) for pipelined operation.
  • Byte Write capability.
  • Single 3.3V power supply.
  • 3.3V/2.5V I/O power supply.
  • Fast clock-to-output times.

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