CY7C1371KV33
Features
- No Bus Latency (No BL) architecture eliminates dead cycles between write and read cycles
- Supports up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin-patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow through operation
- Byte write capability
- 3.3 V/2.5 V I/O power supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
- Clock enable (CEN) pin to enable clock and suspend operation
- Synchronous self-timed writes
- Asynchronous output enable
- Available in JEDEC-standard Pb-free 100-pin TQFP packages
- Three chip enables for simple depth expansion
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