CY7C1371S Overview
The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion. The CY7C1371S is equipped with the advanced No Bus Latency (NoBL) logic required to enable consecutive Read/Write operations with data being transferred on every clock cycle.
CY7C1371S Key Features
- No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
- Supports up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Pin-patible and functionally equivalent to ZBT™ devices
- Internally self-timed output buffer control to eliminate the need
- Registered inputs for flow through operation
- Byte Write capability
- 3.3 V/2.5 V I/O power supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
