CY7C1371S sram equivalent, 18-mbit (512k x 36) flow-through sram.
* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Da.
The CY7C1371S is a 3.3 V, 512K × 36 Synchronous flow through Burst SRAM designed specifically to support unlimited true back-to-back Read/Write operations with no wait state insertion. The CY7C1371S is equipped with the advanced No Bus Latency (NoBL).
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