CY7C1371DV25
Key Features
- No Bus Latency™ (NoBL™) architecture eliminates dead cycles between write and read cycles
- Can support up to 133-MHz bus operations with zero wait states
- Data is transferred on every clock
- Internally self-timed output buffer control to eliminate the need to use OE
- Registered inputs for flow-through operation
- 2.5V core power supply (VDD)
- 2.5V I/O power supply (VDDQ)
- Fast clock-to-output times
- 6.5 ns (for 133-MHz device)
- Clock Enable (CEN) pin to enable clock and suspend operation
