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Cypress Semiconductor Electronic Components Datasheet

CY7C1371DV25 Datasheet

(CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM

No Preview Available !

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CY7C1373DV25
18-Mbit (512K x 36/1M x 18)
Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description[1]
No Bus Latency(NoBL) architecture eliminates
dead cycles between write and read cycles
• Can support up to 133-MHz bus operations with zero
wait states
— Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Registered inputs for flow-through operation
• Byte Write capability
• 2.5V core power supply (VDD)
• 2.5V I/O power supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self-timed writes
• Asynchronous Output Enable
• Available in JEDEC-standard lead-free 100-Pin TQFP,
lead-free and non-lead-free 119-Ball BGA and 165- Ball
FBGA package.
• Three chip enables for simple depth expansion
• Automatic Power-down feature available using ZZ
mode or CE deselect
• IEEE 1149.1 JTAG-Compatible Boundary Scan
• Burst Capability—linear or interleaved burst order
• Low standby power
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
The CY7C1371DV25/CY7C1373DV25 is a 2.5V, 512K x
36/1M x 18 Synchronous Flow-through Burst SRAM designed
specifically to support unlimited true back-to-back Read/Write
operations without the insertion of wait states. The
CY7C1371DV25/CY7C1373DV25 is equipped with the
advanced No Bus Latency (NoBL) logic required to enable
consecutive Read/Write operations with data being trans-
ferred on every clock cycle. This feature dramatically improves
the throughput of data through the SRAM, especially in
systems that require frequent Write-Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock cycle.
Maximum access delay from the clock rise is 6.5 ns (133-MHz
device).
Write operations are controlled by the two or four Byte Write
Select (BWX) and a Write Enable (WE) input. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
133 MHz
6.5
210
70
100 MHz
8.5
175
70
Unit
ns
mA
mA
Notes:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05557 Rev. *D
Revised June 29, 2006


Cypress Semiconductor Electronic Components Datasheet

CY7C1371DV25 Datasheet

(CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM

No Preview Available !

1
Logic Block Diagram – CY7C1371DV25 (512K x 36)
A0, A1, A
MODE
CLK C
CEN
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
ADV/LD
BWA
BWB
BWC
BWD
WE
OE
CE1
CE2
CE3
ZZ
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
READ LOGIC
SLEEP
CONTROL
CY7C1371DV25
CwYw7wC.Da1ta3S7he3eDt4UV.c2om5
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
DQPC
DQPD
2
Logic Block Diagram – CY7C1373DV25 (1M x 18)
A0, A1, A
MODE
CLK C
CEN
CE
ADDRESS
REGISTER
A1
A0
D1
D0
ADV/LD
C
WRITE ADDRESS
REGISTER
Q1
Q0
A1'
A0'
BURST
LOGIC
ADV/LD
BWA
BWB
WE
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
OE
CE1
READ LOGIC
CE2
CE3
ZZ
SLEEP
CONTROL
INPUT E
REGISTER
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
NE
G
DQs
DQPA
DQPB
Document #: 38-05557 Rev. *D
Page 2 of 28


Part Number CY7C1371DV25
Description (CY7C1371DV25 / CY7C1373DV25) Flow-Through SRAM
Maker Cypress Semiconductor
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CY7C1371DV25 Datasheet PDF






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Cypress Semiconductor





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