CY7C1371D sram equivalent, 18-mbit (512 k x 36/1 m x 18) flow-through sram.
* No Bus Latency (NoBL) architecture eliminates dead cycles between write and read cycles
* Supports up to 133-MHz bus operations with zero wait states
* Da.
The CY7C1371D/CY7C1373D is a 3.3 V, 512 K × 36/1 M × 18 synchronous flow through burst SRAM designed specifically to support unlimited true back-to-back read/write operations with no wait state insertion. The CY7C1371D/CY7C1373D is equipped with the .
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