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CDCVF2510A - 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Datasheet Summary

Description

The CDCVF2510A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

The CDCVF2510A uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

Features

  • 1.
  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1.
  • Spread Spectrum Clock Compatible.
  • Operating Frequency 20 MHz to 175 MHz.
  • Static Phase Error Distribution at 66 MHz to 166 MHz is ±125 ps.
  • Jitter (cyc.
  • cyc) at 66 MHz to 166 MHz is |70| ps.
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption vs Current Generation PC133 Devices.
  • Auto Frequency Detection to Disable Devi.

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Datasheet preview – CDCVF2510A

Datasheet Details

Part number CDCVF2510A
Manufacturer Texas Instruments
File Size 425.08 KB
Description 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet download datasheet CDCVF2510A Datasheet
Additional preview pages of the CDCVF2510A datasheet.

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Full PDF Text Transcription

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CDCVF2510A www.ti.com ............................................................................................................................................... SCAS764C – MARCH 2004 – REVISED FEBRUARY 2009 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE FEATURES 1 • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.
Published: |