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CDCVF2509A - 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Datasheet Summary

Description

The CDCVF2509A is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Features

  • 1.
  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1.
  • Spread Spectrum Clock Compatible.
  • Operating Frequency 20 MHz to 175 MHz.
  • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps.
  • Jitter (cyc - cyc) at 60 MHz to 175 MHz Is Typ = 65 ps.
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices.
  • Auto Frequency Detection to Disable De.

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Datasheet preview – CDCVF2509A

Datasheet Details

Part number CDCVF2509A
Manufacturer Texas Instruments
File Size 403.57 KB
Description 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet download datasheet CDCVF2509A Datasheet
Additional preview pages of the CDCVF2509A datasheet.

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Full PDF Text Transcription

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CDCVF2509A www.ti.com SCAS765E – APRIL 2004 – REVISED FEBRUARY 2010 3.3-V PHASE-LOCK LOOP CLOCK DRIVER WITH POWER DOWN MODE Check for Samples: CDCVF2509A FEATURES 1 • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.
Published: |