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CDCVF2510 - 3.3-V PHASE-LOCK LOOP CLOCK DRIVER

Datasheet Summary

Description

The CDCVF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver.

It uses a phase-lock loop (PLL) to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.

It is specifically designed for use with synchronous DRAMs.

Features

  • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.1.
  • Spread Spectrum Clock Compatible.
  • Operating Frequency 50 MHz to 175 MHz.
  • Static Phase Error Distribution at 66 MHz to 166 MHz Is ±125 ps.
  • Jitter (cyc - cyc) at 66 MHz to 166 MHz Is |70| ps.
  • Advanced Deep Submicron Process Results in More Than 40% Lower Power Consumption Versus Current Generation PC133 Devices.
  • Available in Plastic 24-Pin TSSOP.

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Datasheet preview – CDCVF2510

Datasheet Details

Part number CDCVF2510
Manufacturer Texas Instruments
File Size 415.57 KB
Description 3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Datasheet download datasheet CDCVF2510 Datasheet
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Full PDF Text Transcription

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CDCVF2510 www.ti.com SCAS638C – JULY 2001 – REVISED APRIL 2006 3.3-V PHASE-LOCK LOOP CLOCK DRIVER FEATURES • Designed to Meet and Exceed PC133 SDRAM Registered DIMM Specification Rev. 1.
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