Si53208 Datasheet PDF (Low Power Gen 1 to Gen 6 Clock Buffer)

Si53208 - Low Power Gen 1 to Gen 6 Clock Buffer

This page provides the datasheet information for the Si53208, a member of the Si53212 Low Power Gen 1 to Gen 6 Clock Buffer family.

Description

The Si53212, Si53208, and Si53204 are the industry’s highest performance, low additive jitter, low power PCIe clock fanout buffer family that can source 4, 8, or 12 clock outputs.

Features

4, 8, and 12 Output 100 MHz PCIe Gen1 through Gen 6, compliant clock fanout buffer.
Low additive jitter: 0.02 ps rms max, Gen 6.
Low-power, push-pull, HCSL compatible  differential outputs.
10 MHz to 200 MHz clock input.
Individual hardware control pins and I2C controls for Output Enable.
Spread spectrum tolerant to pass through a spread input clock for EMI reduction.
Supports Intel QPI/UPI standards.
Single 1.5 to 1.8 V p.

Datasheet Details

Part number	Si53208
Manufacturer	Skyworks
File Size	1.17 MB
Description	Low Power Gen 1 to Gen 6 Clock Buffer
Datasheet	Si53208 Datasheet
Additional preview pages of the Si53208 datasheet.

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Full PDF Text Transcription

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DATA SHEET Si53212, Si53208, and Si53204: 12/8/4-Output PCI-Express Low Jitter, Low Power Gen 1 to Gen 6 Clock Buffer Applications • Data centers • Servers • Storage • PCIe add-on cards • Communications • Industrial Key Features • 4, 8, and 12 Output 100 MHz PCIe Gen1 through Gen 6, compliant clock fanout buffer • Low additive jitter: 0.02 ps rms max, Gen 6 • Low-power, push-pull, HCSL compatible  differential outputs • 10 MHz to 200 MHz clock input • Individual hardware control pins and I2C controls for Output Enable • Spread spectrum tolerant to pass through a spread input clock for EMI reduction • Supports Intel QPI/UPI standards • Single 1.5 to 1.

Published: Nov 12, 2023 |