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Si5322
PIN-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Features
Not recommended for new
Dual clock outputs with
designs. For alternatives, see the selectable signal format:
Si533x family of products.
LVPECL, LVDS, CML, CMOS
Selectable output frequencies Support for ITU G.709 FEC ratios ranging from 19.44 to 1050 MHz (255/238, 255/237, 255/236)
Low jitter clock outputs with jitter LOS alarm output
generation as low as 0.6 psRMS Pin-programmable settings
(50 kHz–80 MHz)
On-chip voltage regulator for
Integrated loop filter with
1.8 V ±5%, 2.5 or 3.3 V ±10%
selectable loop bandwidth
operation
(150 kHz to 1.