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Si5325 - uP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER

Features

  • Not recommended for new.
  • Dual clock outputs with designs. For alternatives, see the selectable signal format Si533x family of products. (LVPECL, LVDS, CML, CMOS).
  • Generates frequencies from.
  • Support for ITU G.709 and 2 kHz to 945 MHz and select custom FEC ratios (255/238, frequencies to 1.4 GHz from an 255/237, 255/236) input frequency of 10 to 710 MHz.
  • LOS, FOS alarm outputs.
  • Low jitter clock outputs with jitter generation as low as 0.5 ps r.

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Datasheet preview – Si5325

Datasheet Details

Part number Si5325
Manufacturer Silicon Laboratories
File Size 1.38 MB
Description uP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER
Datasheet download datasheet Si5325 Datasheet
Additional preview pages of the Si5325 datasheet.

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Full PDF Text Transcription

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Si5325 µP-PROGRAMMABLE PRECISION CLOCK MULTIPLIER Features  Not recommended for new  Dual clock outputs with designs. For alternatives, see the selectable signal format Si533x family of products. (LVPECL, LVDS, CML, CMOS)  Generates frequencies from  Support for ITU G.709 and 2 kHz to 945 MHz and select custom FEC ratios (255/238, frequencies to 1.4 GHz from an 255/237, 255/236) input frequency of 10 to 710 MHz LOS, FOS alarm outputs    Low jitter clock outputs with jitter generation as low as 0.5 ps rms  (12 kHz–20 MHz)  Integrated loop filter with selectable loop bandwidth (150 kHz to 2 MHz)  Dual clock inputs w/manual or automatically controlled  I2C or SPI programmable On-chip voltage regulator for 1.8 ±5%, 2.5 or 3.
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