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K4D263238M - 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM

General Description

The K4D263238 is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • 2.5V ± 5% power supply.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3,4 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave).
  • Full page burst length for sequential burst type only.
  • Start address of the full page burst should be even.
  • All inputs except data & DM are sampled at the positive going edge of the system clock.
  • Different.

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Full PDF Text Transcription for K4D263238M (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4D263238M. For precise diagrams, and layout, please refer to the original PDF.

K4D263238M 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous RAM with Bi-directional Data Strobe and DLL Revision 1.3 August 2001 Samsung...

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th Bi-directional Data Strobe and DLL Revision 1.3 August 2001 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 1.3 (Aug. 2001) K4D263238M Revision History Revision 1.3 (August 2, 2001) • Removed K4D263238M-QC40 with VDD&VDDQ=2.8V • Changed VDD&VDDQ of K4D263238M-QC45 from 2.8V to 2.5V. • Changed tCK(max) from 7ns to 10ns. 128M DDR SDRAM Revision 1.2 (July 12, 2001) • Corrected CAS latency of K4D263238M-QC45 from CL3 to CL4 • The specification for the 222MHz/250MHz is preliminary one. Revision 1.1 (March 5, 2000) • Added K4D263238M-QC40 with VDD&VDDQ=2.8V • Changed VDD/V

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