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K4D263238A - 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM

General Description

The K4D263238A is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Key Features

  • 2.5V + 5% power supply for device operation.
  • 2.5V + 5% power supply for I/O interface.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3,4,5 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave).
  • Full page burst length for sequential burst type only.
  • Start address of the full page burst should be even.
  • All inputs except data & DM are.

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Full PDF Text Transcription for K4D263238A (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4D263238A. For precise diagrams, and layout, please refer to the original PDF.

K4D263238A-GC 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 2.0...

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M with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 2.0 January 2003 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev. 2.0 (Jan. 2003) K4D263238A-GC Revision History Revision 2.0 (January 16, 2002) • Changed package ball height from 0.25mm to 0.35mm • Typo corrected 128M DDR SDRAM Revision 1.9 (July 18, 2002) • Changed power dissipation from 2.0W to 2.3W Revision 1.8 (June 12, 2002) • Supported both CL4 and CL3 for the K4D263238A-GC45 and the effective date of this change starts from WW23 Revision 1.6 (January 30, 2002) • Changed tCK(max) of K4D263238A-GC40

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