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K4D263238E - 1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM

General Description

The K4D263238E is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x1,048,576 words by 32 bits, fabricated with SAMSUNG’s high performance CMOS technology.

Key Features

  • VDD/VDDQ = 2.8V ± 5% for -GC25.
  • VDD/VDDQ = 2.5V ± 5% for -GC2A/33/36/40/45.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3, 4, 5 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave).
  • Full page burst length for sequential burst type only.
  • Start address of the full page burst should be even.
  • All inputs except data & DM are sampled a.

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Full PDF Text Transcription for K4D263238E (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4D263238E. For precise diagrams, and layout, please refer to the original PDF.

K4D263238E-GC 128M GDDR SDRAM 128Mbit GDDR SDRAM 1M x 32Bit x 4 Banks Graphic Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Re...

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ronous DRAM with Bi-directional Data Strobe and DLL (144-Ball FBGA) Revision 1.7 November 2003 Samsung Electronics reserves the right to change products or specification without notice. - 1 - Rev 1.7 (Nov. 2003) K4D263238E-GC Revision History Revision 1.7 (November 14, 2003) • Typo corrected 128M GDDR SDRAM Revision 1.6 (August 14, 2003) • Added a note for the input reference voltage of clock in case of differential clocks Revision 1.5 (August 11, 2003) • Typo corrected Revision 1.4 (April 30, 2003) • Added Lead free package part number in the datasheet Revision 1.3 (April 14, 2003) • K4D263238E-GC2A/33/36 support wide vol

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