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K4D263238F - 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM

General Description

The K4D263238F is 134,217,728 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Key Features

  • 2.5V ± 5% power supply for device operation.
  • 2.5V ± 5% power supply for I/O interface.
  • SSTL_2 compatible inputs/outputs.
  • 4 banks operation.
  • MRS cycle with address key programs -. Read latency 3 (clock) -. Burst length (2, 4, 8 and Full page) -. Burst type (sequential & interleave).
  • Full page burst length for sequential burst type only.
  • Start address of the full page burst should be even.
  • All inputs except data & DM are samp.

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Full PDF Text Transcription for K4D263238F (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for K4D263238F. For precise diagrams, and layout, please refer to the original PDF.

K4D263238F 128M DDR SDRAM 128Mbit DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL Revision 1.1 May 2003 - 1 - Rev...

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ith Bi-directional Data Strobe and DLL Revision 1.1 May 2003 - 1 - Rev 1.1 (May 2003) K4D263238F Revision History Revision 1.1 (May 30, 2003) • Added Lead Free package part number in the datasheet. 128M DDR SDRAM Revision 1.0 (April 29, 2003) • Define DC spec. Revision 0.0 (January 20, 2003)- Target spec • Define target spec. - 2 - Rev 1.1 (May 2003) K4D263238F 128M DDR SDRAM 1M x 32Bit x 4 Banks Double Data Rate Synchronous DRAM with Bi-directional Data Strobe and DLL FEATURES • 2.5V ± 5% power supply for device operation • 2.5V ± 5% power supply for I/O interface • SSTL_2 compatible inputs/outputs • 4 banks operation • M

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