Datasheet4U Logo Datasheet4U.com

NT5CB256M8JQ - Commercial and Industrial DDR3(L) 2Gb SDRAM

Datasheet Summary

Features

  • JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
  • Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
  • Power Saving Mode - Power Down Mode.
  • Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
  • Signal Synchroniza.

📥 Download Datasheet

Datasheet preview – NT5CB256M8JQ

Datasheet Details

Part number NT5CB256M8JQ
Manufacturer Nanya
File Size 3.54 MB
Description Commercial and Industrial DDR3(L) 2Gb SDRAM
Datasheet download datasheet NT5CB256M8JQ Datasheet
Additional preview pages of the NT5CB256M8JQ datasheet.
Other Datasheets by Nanya

Full PDF Text Transcription

Click to expand full text
NTC Proprietary Level: Property DDR3(L)-2Gb J-Die NT5CB(C)256M8JQ/NT5CB(C)128M16JR Commercial and Industrial DDR3(L) 2Gb SDRAM Features  JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Power Down Mode  Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Signal Synchronization - Write Leveling via MR settings 5 - Read Leveling via MPR  Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1353 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.
Published: |