NT5CB256M16CP - Industrial and Automotive DDR3(L) 4Gb SDRAM

This page provides the datasheet information for the NT5CB256M16CP, a member of the NT5CB512M8CN Industrial and Automotive DDR3(L) 4Gb SDRAM family.

Datasheet Summary

The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM containing 4,294,967,296 bits.

It is internally configured as an octal-bank DRAM.

The 4Gb chip is organized as 64Mbit x 8 I/O x 8 banks and 32Mbit x16 I/O x 8 banks.

JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/ ) - Double-data rate on DQs, DQS and DM.
Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Signal Synchronization - Write Leveling via MR settings -.

Nanya

Part number	NT5CB256M16CP
Manufacturer	Nanya
File Size	3.88 MB
Description	Industrial and Automotive DDR3(L) 4Gb SDRAM
Datasheet	NT5CB256M16CP Datasheet
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DDR3(L) 4Gb SDRAM NT5CB(C)512M8CN / NT5CB(C)256M16CP Nanya Technology Corp.

Published: Mar 24, 2014 |