IS42SM32100C Datasheet PDF - ISSI 512K x 32Bits x 2Banks Low Power Synchronous DRAM Specs

IS42SM32100C - 512K x 32Bits x 2Banks Low Power Synchronous DRAM

Datasheet Summary

Description

These IS42SM/RM/VM32100C are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits.

These products are offering fully synchronous operation and are referenced to a positive edge of the clock.

Features

JEDEC standard 3.3V, 2.5V, 1.8V power supply.
Auto refresh and self refresh.
All pins are compatible with LVCMOS interface.
4K refresh cycle / 64ms.
Programmable Burst Length and Burst Type. - 1, 2, 4, 8 or Full Page for Sequential Burst. - 4 or 8 for Interleave Burst.
Programmable CAS Latency : 2,3 clocks.
Programmable Driver Strength Control - Full Strength or 1/2, 1/4, 1/8 of Full Strength.
Deep Power Down Mode.

Datasheet Details

Part number	IS42SM32100C
Manufacturer	ISSI
File Size	1.85 MB
Description	512K x 32Bits x 2Banks Low Power Synchronous DRAM
Datasheet	IS42SM32100C Datasheet
Additional preview pages of the IS42SM32100C datasheet.

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Full PDF Text Transcription

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IS42SM32100C IS42RM32100C IS42VM32100C 512K x 32Bits x 2Banks Low Power Synchronous DRAM Description These IS42SM/RM/VM32100C are low power 33,554,432 bits CMOS Synchronous DRAM organized as 2 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features  JEDEC standard 3.3V, 2.5V, 1.8V power supply. • Auto refresh and self refresh. • All pins are compatible with LVCMOS interface. • 4K refresh cycle / 64ms. • Programmable Burst Length and Burst Type.

Published: Oct 22, 2013 |