IS42S16128 - 128K words x 16 Bits x 2 Banks SDRAM

Datasheet Summary

Description

PIN DESCRIPTIONS A0-A9 A0-A8 A9 A0-A7 I/O0 to I/O15 CLK CKE CS RAS CAS WE LDQM UDQM Address Input Row Address Input Bank Select Address Column Address Input Data I/O System Clock Input Clock Enable Chip Select Row Address Strobe Command Column Address Strobe Command Write Enable Lower Bye, Input/Out

Features

Clock frequency: 125 MHz, 100 MHz, 83 MHz.
Two banks can be operated simultaneously and independently.
Single 3.3V power supply.
LVTTL interface.
Programmable burst length.
(1, 2, 4, 8, full page).
Programmable burst sequence: Sequential/Interleave.
Auto refresh, self refresh.
1K refresh cycles every 16 ms.
Random column address every clock cycle.
Programmable CAS latency (2, 3 clocks).
B.

Integrated Silicon

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Datasheet Details

Part number	IS42S16128
Manufacturer	Integrated Silicon
File Size	638.47 KB
Description	128K words x 16 Bits x 2 Banks SDRAM
Datasheet	IS42S16128 Datasheet
Additional preview pages of the IS42S16128 datasheet.

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Full PDF Text Transcription

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IS42S16128 128K Words x 16 Bits x 2 Banks (4-MBIT) SYNCHRONOUS DYNAMIC RAM FEATURES • Clock frequency: 125 MHz, 100 MHz, 83 MHz • Two banks can be operated simultaneously and independently • Single 3.

Published: Jul 19, 2005 |