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IS42SM32200M - 512K x 32Bits x 4Banks Mobile Synchronous DRAM

This page provides the datasheet information for the IS42SM32200M, a member of the IS42VM32200M 512K x 32Bits x 4Banks Mobile Synchronous DRAM family.

Datasheet Summary

Description

These IS42SM/RM/VM32200M are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits.

These products are offering fully synchronous operation and are referenced to a positive edge of the clock.

Features

  • JEDEC standard 3.3V, 2.5V, 1.8V power supply.
  • Auto refresh and self refresh.
  • All pins are compatible with LVCMOS interface.
  • 4K refresh cycle / 64ms.
  • Programmable Burst Length and Burst Type - 1, 2, 4, 8 or Full Page for Sequential Burst - 4 or 8 for Interleave Burst.
  • Programmable CAS Latency : 2,3 clocks.
  • All inputs and outputs referenced to the positive edge of the system clock.
  • Data mask function by DQM.
  • Internal 4.

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Datasheet preview – IS42SM32200M

Datasheet Details

Part number IS42SM32200M
Manufacturer ISSI
File Size 856.23 KB
Description 512K x 32Bits x 4Banks Mobile Synchronous DRAM
Datasheet download datasheet IS42SM32200M Datasheet
Additional preview pages of the IS42SM32200M datasheet.

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IS42/45SM/RM/VM32200M 512K x 32Bits x 4Banks Mobile Synchronous DRAM Description These IS42SM/RM/VM32200M are mobile 67,108,864 bits CMOS Synchronous DRAM organized as 4 banks of 524,288 words x 32 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve high bandwidth. All input and output voltage levels are compatible with LVCMOS. Features  JEDEC standard 3.3V, 2.5V, 1.
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